>>108903682
basically it's like when you fold a piece of paper and stick a pen through it to connect the folded halves but with logic instead of spacetime and without time travel

Sounds like the same idea as 3D packages, but instead of each layer being a chiplet with an interconnect bus it's instead splitting the logic and directly connecting logic paths between layers. The idea being that you can have the same CPU logic, but with shorter connections.

Which, sure. Kudos if they can get it to work. Layout sounds like a bitch. Porbably good they're doing this with the old fab tech they have to use, I doubt this'd hold up with smaller processes.

>>108903682
This sounds like it would have thermal issues and still be n-times as expensive where n is the number of layers.

>>108903682
It's like 2.6D instead of the usual 2.5D design (stacked 2D, like classic Mario).

>>108903751
They're claiming that they can achieve 238 MTr/mm (million transistors per square millimeter) in their latest Kirin chip which will be released in Q4 2026, which is equivalent to N3P "3nm" from TSMC or Intel's 18A

Based

>>108903854
It's still a larger process. They're achieving the equivalent density by having a sparser technology stacked in layers. If you took 3nm and did this, you'd have even denser transistor packing. But like I said, I doubt you're be able to do something like this efficiently in a smaller process.