>modern CISC (Complex Instruction Set Computer) chips like x86 internally translate complex instructions into streamlined, RISC-like micro-operations, eliminating the historical power penalty of the instruction setEvery Intel or AMD processor bullt today is a RISC engine at its core. Pipelining, out-of-order execution, speculative execution, and large register files are all fundamental RISC principles. The pure hardware managed CISC execution model is dead.
>>109470317x86 was always RISC, the 8086 had a RISC core. In fact, modern x86 cpus are less risc than the 8086 since out of order micro-ops are not really instructions. Whilst the 8086 micro-ops are quite literally an internal RISC instruction set with a program counter.
>>109470317Do you really think people cares about RISC vs CISC? They don't what I see when I see the ISA is that x86 and (x86-64) has a lot of historical baggage and incidental complexity while modern "RISC" is more orthogonal and ergonomic, of course only compiler writers care about this, but elegance should not be ignored. The only relevant thing now is microachitecture.
Apple buck broke CISC bros, both Intel and AMD will eventually take the L
RISC processors like SPARC had already BTFOd CISC during early 90s, back then Intel COPEd by launching Pentium Pro, which was the first processor that could dynamically translate CISC instructions into RISC-like micro-operations.Intel successfully leveraged its larger scaling capability and x86 software moat to win, but now with ARM becoming the normal across the aisle, software is no longer the issue.
>>109470317thank you, cock!JOHN COCK!
>>109472354thank you for inventing cocks, mr John Cocke
We're having one of these threads again?>>109470317>Every Intel or AMD processor bullt (sic) today is a RISC engine at its core.You're retarded (and ESL). CISC instructions existing in hardware means they can be made much faster than the equivalent sequence of RISC operations.>Pipelining, out-of-order execution, speculative execution, and large register files are all fundamental RISC principles.No, they're just good ideas. They have nothing to do with instructions not being able to both access memory and do computation.>>109470560Quite a lot of that "historical baggage" are things that are quite nice to have, eg. read-modify-write instructions, an extremely compact instruction encoding scheme providing good cache utilization, variable-length instructions in general, and strong memory ordering making multithreading much easier and more performant.
>>109470317Anyone saying this don’t know shit about either CISC nor RISC.
no one care about the internal architecture. risc is about reducing the complexity at the cpu level to raise it at the compiler level. modern x86 cpu are still cisc from the outside and thus compilers are still translating to a cisc architecture. also, modern risc cpus are now SoC with all kind of co processors (video encoding, photo encoding, gpu, audio DSP, ...), each having its own instruction set: instead of having one instruction set you now have ten.
>>109470317>modern CISC (Complex Instruction Set Computer) chips like x86 internally translate complex instructions into streamlined, RISC-like micro-operations, eliminating the historical power penalty of the instruction setRetard asked a question to literally any LLM and got this answer. This doesn't mean x86 is RISC. It's still CISC. Nobody cares what CPU does while decoding instructions.Now go back to asking ChatGPT if this is true.
>>109470713i would like to hear CD10B7B88EDBAC83EE393004E661EBF6 (80286, 16MHz, MSdos) in the same size (16 bytes, 8 instructions) on an ARM chip.
CD10B7B88EDBAC83EE393004E661EBF6
>>109472958see this >>109470713 and COPE
>>109472919> raise it at the compiler levelThis more complex compiler nonsense stopped applying before most people in this thread were born. The only point in history that applied was in single pass compilers that produced machine code directly with basically zero optimizations.
