>turning one instruction into twelveSo this is the power of RISC
>>107539017The reason why RISCV is so slow right now is because it is lacking good branch prediction, in comparison lack of compound instructions is a minor performance hit
>>107539051That's AArch64 asm in the screenshot.RISC-V is even worse since the AES instructions don't use the vector registers at all.
>>107539017What do you think "reduced instruction set" meansWould you prefer to have six gorillion obscure instructions like amd64
>>107539017now show the actual circuits and power required to process said 'single instruction' vs the arm one
Not a single RISC architecture has a CAS instruction except RISC-V which only has it as an extra nobody will implement. The day I learned that, I immediately grew out of the RISC meme.
>>107539017Kind of a moot point, cause all modern x86_64 processors implement a smaller RISC-like language for implementing the big instructions called micro-code. They define the individual atomic operations used for operations, because past a certain point it became infeasible to maintain all of x86’s op-codes in pure silicon, and microcode also means you can fix bugs
>>107540419You’re wrong, ARM has one: https://developer.arm.com/documentation/ddi0602/2025-09/Base-Instructions/CAS--CASA--CASAL--CASL--Compare-and-swap-word-or-doubleword-in-memory-RISC-V also has a standard extension that implements it, but it’s not part of the base standard
>>107539017There is nothing even remotely "reduced" about modern ARM. Also, ARM does not have 512bit registers, so obviously it would need multiple instructions. Nothing whatsoever to do with being "RISC".
>>107540337>Would you prefer to have six gorillion obscure instructions like amd64lollmaokek, even
>>107540559My understanding is that the RISC model mostly focuses on making sure an instruction does one thing. This means that instructions do not handle storing to memory, or fetching from memory. You need to do this yourself. So every instruction is preceded by loads and succeeded by stores. CISC architectures on the other hand have more complex instruction encodings, that mean that any given instruction can:- Read from a register, write to a static address - Read from a register, write to an address in another register- Read from a register, write to a registerAnd so on. This encoding is a notable factor in the complexity of x86, because of just how many ways these can be combined. Doing it like this makes it easier for human devs, because it’s less verbose and easier to work with, which is why x86 won out I think, cause at the time a lot more people were writing directly in assembly.
>>107539051>it is lacking good branch predictionRather than guessing the next instruction, the CPU should just guess the final output. We can call it "predictive computing". You don't even need to write a program, just a vague statement of what you're kinda looking for.
>>107540624Maybe some fags will make AI do it
>>107540604>an instruction does one thingYes, it works like traditional CPUs used to work. REDUCED Instruction Set Computing...i.e. the total number of registers is deliberately limited. This gives you granular control over program execution but requires hand-optimization of code. It CAN be better, but it won't be if you're using jeetcoders.CISC treats registers as more of an API, where a call to a register may result in the computer performing numerous additional steps not specified in the program. Such as CMPXCHG and XADD. The idea being that you can improve performance by having commonly used operations baked into the hardware rather than having to repeat them via software step-by-step each time.
>>107540629And make it slower than a 68k whilst requiring Guatemala's total power output to compute a single SHA512 hash.
>>107540440Compilers still rely on LS/SC retardation.https://godbolt.org/z/1rGr1fMjr
>>107540704Yep, and they'll boast about it too and hype retarded investors up with it.
>>107539017>turning one instruction into twelveyou're describing Intel's microcode
>>107540824Except the microcode doesn't unroll into every nook and cranny of the platform, bloating every executable N-fold.
>>107540738armv7 doesn’t appear to have it, changing the compiler to ARM64 GCC uses the casal instruction: https://godbolt.org/z/resrT3c8h
>>107540704>than a 68kzoomer spotted
>>107539017From what I see, vaesenc has a latency of 4 to 5 while aese could be run concurrently on separate ALUs.
>>107540910>>than a 68k>zoomer spottedI specifically using a 68k because it is widely considered to have the cleanest microcode whilst still being fairly performant. This simplicity would make it a likely target for any ml training since it is vastly simply than x86, and thus, would have fewer output errors, and it is even still supported by gcc. Aside from that, expecting an ai model made to simulate a cpu to avoid branching is unlikely to be doable much faster than that; I should be shocked if it even reached Pentium speeds.
>>107541042but it has both microcode and nanocode
>>107541113I didn't say it was clean--just cleanest (esp. vs amd64) while still having decades of tooling and modern support. RISCV is still shitty and fragmented without as much support.
>>107540559>Almost 50% more instructions>Almost three times longer manual>Still has been performance/watt and battery life than anything else on the market
>>107541172>performance/wattNot really, when you consider work done per unit of power x86 shits on everything.
>>107539017>le import solution architecture
>>107540687risc lowers the complexity at the circuitry level but raises it at the compiler level. Modern "risc" cpus also have a lot of instructions or are surrounded which a bunch of coprocessors. Smartphones, for example, have co-processors for photography, video recording, video decoding, audio processing, AI, rendering (gpu), encryption, ... instead of having a large instruction set, you have multiple ones to handle. From an user (programmer) perspective: cisc >>> risc.
>>107541318>user (programmer)user (user) as well, x86 is compatible with everything, arm is not.
>>107539017>ahhhhh aesKYS
>>107541429No.
https://www.youtube.com/watch?v=vJP_oKN4Ez0
>>107540424>Kind of a moot point, cause all modern x86_64 processors implement a smaller RISC-like language for implementing the big instructions called micro-code.So did the 8086.https://www.righto.com/2022/11/how-8086-processors-microcode-engine.html>>107540687>Yes, it works like traditional CPUs used to work. REDUCED Instruction Set ComputingIt's the other way around. Traditional CPUs are CISC and have microcode.
>>107540629Yes what we really need is for CPUs to hallucinate
>>107541809Marketing execs: "But AI doesn't hallucinate! It gives the correct answer that nobody else can!"
>>107541318RISC is a myth, it basically does not exist in practice. There is nothing even remotely reduced about a modern ARM core.
>>107542008MIPS was
>>107541429elaborate, retarded gorilla nigger
