>>108564876
process(clk, rstn)
variable tmp_sio_out : std_logic_vector(7 downto 0);
variable idx_v : integer;
begin
if rstn = '0' then
elsif rising_edge(clk) then
ack <= '0';
case curr_state is
when ST_IDLE =>
sio_oe <= '0';
csn_i <= '1';
[...]
if req = '1' then
[...]
if we = '1' then
wdata_reg <= wdata;
cmd_data_reg <= SPI_QUAD_WRITE;
else
cmd_data_reg <= SPI_QUAD_READ;
end if;
curr_state <= ST_CMD;
end if;
when ST_CMD =>
csn_i <= '0';
sio_oe <= '1';
[...]
when ST_ADDR =>
[...]
if bit_cnt = 0 then
if we_reg = '1' then
bit_cnt <= 3;
sio_oe <= '1';
curr_state <= ST_WRITE;
else
bit_cnt <= RD_WAIT_CYCLES-1;
-- sio_oe <= '0'; WRONG!
curr_state <= ST_WAIT;
end if;
end if;
when ST_WAIT =>
sio_oe <= '0'; -- based
[...]
when ST_WRITE => [...]
when ST_READ =>
when ST_ACK => [...]
end case;
end if;
end process;
If anyone wants to know:
The sio_oe signal going low had to be moved from ST_ADDR to ST_WAIT such that the last addr nibble will still get output on the next clock cycle.
