Any VHDL fag here?
I am trying to implement SPI in VHDL (currently the slave) and I feel like I don't really understand some signal handling.
I want to only watch for SCLK when nCS is 0. ChatGPT told me something like this:
process(SCLK, nCS)
begin
if nCS = '0' then
-- Clock edge detection and data latching only when nCS is active
if rising_edge(SCLK) then
-- Handle data capture or processing on the rising edge
end if;
end if;
end process;
Is this "good" VHDL kode? I've never seen something like that to have the rising_edge inside another if