>>108804359
>>108804371
No.
an ADD operation can't be <1 cycle either. There are no half cycles really. You only use both clock edges on shit like DDR or differential signaling.
And for a function call it heavily depends what one means by that.
First you gotta compute and save the jump location into a register. That's why terry used REL32.
Then, if you have no branch prediction or wrong one, then you gotta flush the pipeline. On a classic 5 stage pipeline that's 5 cycles (more on cisc).
Then you gotta save and restore registers. Depending on how many registers you need. Like this:
check_cmds:
# check regs on stack
addi sp, sp, -32
sw ra, 0(sp)
sw s0, 4(sp)
sw s1, 8(sp)
sw s2, 12(sp)
sw s3, 16(sp)
sw s4, 20(sp)
# [...] do niggerlicious stuff [...]
# return
lw s4, 20(sp)
lw s3, 16(sp)
lw s2, 12(sp)
lw s1, 8(sp)
lw s0, 4(sp)
lw ra, 0(sp)
addi sp, sp, 32
ret
Either you do that saving on callee or caller. Doesn't matter that much really. You just gotta pick your registers.
But in general function calls are not expensive.
